1. Field of the Invention
The present invention relates to a MOS type field effect transistor and a manufacturing method thereof and, more particularly, to a MOS type field effect transistor having a channel area provided with thin film and a manufacturing method of such a transistor.
2. Description of the Background Art
It has been recently demanded to establish microtechnology as the density and integration tend to increase in the MOS type field effect transistor (hereinafter abbreviated as "MOSFET") in which a source for supplying a carrier and a drain for taking out the carrier are located on both sides of a capacitor consisting of a metal-oxide film-semiconductor structure provided with a metal electrode on a silicon semiconductor substrate by means of oxide film.
Incidentally, because parasitic capacity is formed inside the MOSFET owing to its structure and the time for charging and discharging of the parasitic capacity determines the operating speed of the MOSFET, it becomes possible to operate the MOSFET at high speed by minimizing the parasitic capacity.
The MOSFET is now required to have a novel structure for achieving high speed operation through miniaturization. As an example of such a novel structure, there is an SOI (Silicon On Insulator) structure in which a channel area is provided with thin film to reduce the parasitic capacity between the source and substrate as well as between the drain and substrate. FIG. 5 is a structural sectional view and a plan view illustrating a conventional n-channel MOSFET having an SOI structure.
In this drawing, the reference numeral (1) indicates a P-type silicon semiconductor substrate having the density of 1.times.10.sup.15 cm.sup.-3 and the specific resistance of 10.OMEGA..cm; numeral (2) indicates an insulator layer formed on one main surface of the foregoing P-type silicon semiconductor substrate(1); numeral (3) indicates a P-type silicon semiconductor layer having the density of 1.times.10.sup.15 cm.sup.-3 and the specific resistance of 10.OMEGA..cm formed on the main surface which does not contact the foregoing P-type silicon semiconductor substrate (1) of the foregoing insulator (2); numeral (4) indicates a channel area having the density of 1.times.10.sup.16 to 1.times.10.sup.17 cm.sup.-3 formed by injecting boron ions into the foregoing P-type silicon semiconductor layer (3) with the acceleration voltage of 10 to 30 Kev and the dose of 1.times.10.sup.12 to 1.times.10.sup.14 cm.sup.-2 ; numeral (5) indicates an n.sup.+ type source area having the density of 1.times.10.sup.19 to 1.times.10.sup.21 cm.sup.-3 formed to cause the bottom thereof to contact the foregoing insulator layer (2) by injecting arsenic ions into the foregoing P-type silicon semiconductor layer (3) with the acceleration voltage of 40 Kev and the dose of 5.times.10.sup.15 cm.sup.-2 ; numeral (6), like the foregoing n.sup.+ type source area (5), indicates an n.sup.+ type drain area having the density of 1.times.10.sup.19 to 1.times.10.sup.21 cm.sup.-3 formed to cause the bottom thereof to contact the foregoing insulator layer (2) by injecting arsenic ions into the foregoing P-type silicon semiconductor layer (3) with the acceleration voltage of 40 Kev and the dose of 5.times.10.sup.15 cm.sup.-2 ; numeral (7) indicates a gate dielectric thin film formed on the main surface which does not contact the foregoing insulator layer (2) of the foregoing P-type silicon semiconductor layer (3); numeral (8) indicates a gate electrode formed on the foregoing gate dielectric thin film (7); numeral (9) indicates a layer insulation film formed to cover the foregoing P-type silicon semiconductor layer (3) and the foregoing gate electrode (8); numeral (10a) is a first contact hole provided on the foregoing n.sup.+ type source area; numeral (10b), like the foregoing first contact hole (10a), indicates a second contact hole provided on the foregoing n.sup.+ type drain area (6); numeral (11a) indicates a first wiring of aluminum alloy formed in the foregoing first contact hole (10a); and (11b), like the foregoing second contact hole (11a), indicates a second wiring of aluminum alloy formed in the foregoing second contact hole (10b).
Since the conventional n channel MOSFET is composed in a manner mentioned above, when a voltage over the threshold is applied to the gate electrode (8), the electron which is the carrier of the n-type semiconductor is drawn toward the surface of the channel area (4), changing the surface into the same n-type as that of the n.sup.+ type source area (5) and the n.sup.+ type drain area (6). Therefore, current flows between the n.sup.+ type source area (5) and the n.sup.+ type drain area (6). Because the density of the carrier drawn to the surface of the channel area (4) varies depending upon the voltage applied to the gate electrode (8), the amount of current flowing through the channel area (4) can be controlled by the voltage to be applied to the gate electrode (8).
(Problems to be solved by the invention) PA0 (Means of Solution to the problems)
In the conventional n-channel MOSFET whose channel area is provided with thin film as mentioned above, if the P-type silicon semiconductor layer (3) is relatively thin (about 5000.ANG.A) and the gap between the n.sup.+ type source area (5) and the n.sup.+ type drain area (6) is reduced, the voltage to be applied to the n.sup.+ type drain area (6) may rise and the depletion layer in the vicinity of the n.sup.+ type drain area (6) may extend up to the n.sup.+ type source area (5). When the depletion layer extends up to the n.sup.+ type source area (5), the electric trouble between the n.sup.+ type source area (5) and the channel area (4) is reduced, and a large amount of current flows out to a deep area (the area of the lower part of 2000 to 4000.ANG.) from the surface of the P-type silicon semiconductor layer (3), resulting in a "punch through" in which the operation of the MOSFET is lost. This punch through restricts the voltage that can be applied to the n.sup.+ type drain area (6), and the dielectric strength between the n.sup.+ type source area (5) and the n type drain area (6) is caused to be reduced.
On the other hand, the voltage that is applied to the n.sup.+ type drain area (6) rises with the resultant increase in the electric field intensity in the P-type silicon semiconductor layer (3), and in particular, a high electric field emerges in the depletion layer in the vicinity of the n.sup.+ type drain area (6). The electron of the channel area (4) is accelerated by the high electric field in the vicinity of this n.sup.+ type drain area (6) and injected into the depletion layer in the vicinity of the n.sup.+ type drain area (6), causing the ionization by collision of the grid of silicon thereby generating a lot of pairs of electron and positive hole. The generated electron is further drawn toward the high electric field in the vicinity of the n.sup.+ type drain area (6) and the most part of the electron flows into the n.sup.+ type drain area (6). In the meantime, the positive hole flows in from the depletion layer in the vicinity of the n.sup.+ type drain area (6) to be accumulated on the bottom of the P-type silicon semiconductor layer (3) which is not depleted, thereby increasing the electric potential, and causing the current to increase suddenly when the lateral NPN transistor, comprising the n.sup.+ type drain area (6) as a collector, the bottom of the P-type silicon semiconductor layer (3) as a base, and the n.sup.+ type source area (5) as an emitter, is made conductive by surmounting the electric potential trouble in the forward direction between the bottom of the P-type silicon semiconductor layer (3) and the n.sup.+ type source area (5). Because the current caused by the conduction of this lateral NPN transistor is added to the current flowing through the ordinary channel area (4), a "kink" effect takes place where bends are specific to the drain current-drain voltage characteristic of the MOSFET as illustrated in FIG. 6. Because such kink effect, like the mentioned punch through, restricts the voltage that can be applied to the n.sup.+ type drain area (6), the dielectric strength between the n.sup.+ type source area (5) and the n.sup.+ type drain area (6) is caused to be reduced.
Now, if the P-type silicon semiconductor layer (3) is thin (500 to 1500.ANG.) and when the gap between the n.sup.+ type source area (5) and the n.sup.+ type drain area (6) is reduced, the voltage to be applied to the n.sup.+ type drain area (6) is increased, the depletion layer in the vicinity of the n.sup.+ type drain area (6) is expanded toward the n.sup.+ type source area (5), and the entirety of the P-type silicon semiconductor layer (3) is made to have a depletion layer. After the P-type silicon semiconductor is provided with the depletion layer, the electric trouble between the P-type silicon semiconductor layer (3) and the n.sup.+ type source area (5) is reduced and the election in the n.sup.+ type source area (5) tries to flow into the depletion layer, but the electron flowing into the depletion layer is controlled by the voltage applied to the gate electrode (8) because the P-type silicon semiconductor layer (3) is thin, thereby allowing the current to flow into the channel area (4) only. Therefore, when the P-type silicon semiconductor layer (3) is thick, there occurs no punch through which causes the current to flow out in the deep area of the depletion layer.
As with the case wherein the P-type silicon semiconductor layer (3) is relatively thick, the voltage that is applied to the n.sup.+ type drain area (6) rises, the electron in the channel area (4) is accelerated by the high electric field appearing in the depletion layer in the vicinity of the n.sup.+ type drain area (6) so as to be injected into the depletion layer in the vicinity of the n.sup.+ type drain area (6), ionization is caused by collision to generate a lot of pairs of electron and positive hole, and the generated electron flows into the n.sup.+ type drain area (6). However, the positive hole flows in from the depletion layer in the vicinity of the n.sup.+ type drain area (6) to be accumlated on the bottom of the P type silicon semiconductor layer (3) wherein the entirety thereof is depleted and floating, thereby increasing the electric potential, and causing the already reduced electric trouble between the P-type silicon semiconductor layer (3) and the n.sup.+ type source are (5) to be reduced further. As a result of further reduced electric trouble between this P-type silicon semiconductor layer (3) and the n.sup.+ type source area (5), the positive hole generated by the ionization caused by collision in the depletion layer is not controlled by the voltage applied to the gate electrode but flows into the n.sup.+ type source area (5) while the electron in the n.sup.+ type source area (5) flows suddenly into the channel area (4) and may cause the current flowing through the channel area (4) to increase.
That is, even if the P type silicon semiconductor layer (3) is thin and when the gap between the n.sup.+ type source area (5) and the n.sup.+ drain area (6) is reduced, the punch through or kink does not occur. However, a problem exists in that the current flowing through the channel area (4) is increased to restrict the voltage that can be applied to the n.sup.+ type drain area (6), whereby a drawback in which the dielectric strength between the n.sup.+ type source area (5) and the n.sup.+ type drain area (6) is caused to be undesirably reduced.
A further problem is involved wherein it is impossible to reduce the gap between the n type source area (5) and the n type drain area (6), making it difficult to promote the miniaturization of the MOSFET.